If you work with Xilnx Vivado Design Suite [1] for FPGA development using USB JTAG interface such as Xilinx USB Platform Cable [2] or its cheaper clone from WaveShare [3], everything seems to be connected properly, but it cannot find the Target for programming, you probably need to perform drivers setup manually [4]. Error message looks like this:

ERROR: [Labtoolstcl 44-494] There is no active target available for server at localhost.
Targets(s) ", jsn3" may be locked by another hw_server.

Error message may indicate that another instance of hw_server is running in the background but that is not the case. Check your drivers first [4]. Some hints:

• Run as root and be careful as this will modify your OS.
• Install script location is Vivado/2020.2/data/xicom/cable_drivers/lin64/install_script/install_drivers.
• Platform Cable USB interface is pcusb.
• Make sure UDEV rules are installed in /etc/udev/rules.d/ (i.e. 52-xilinx-pcusb.rules file).
• After drivers are set up remember to restart UDEV with service udev restart command and re-attach your USB JTAG cable.

[1] https://www.xilinx.com/products/design-tools/vivado.html
[2] https://www.xilinx.com/products/boards-and-kits/hw-usb-ii-g.html
[3] https://www.waveshare.com/platform-cable-usb.htm
[4] https://www.xilinx.com/support/answers/54381.html

I just did a self-assembly of JTAGulator. This simple and amazing device indeed works and shortens JTAG pinout search from days to seconds. AMAZING! I have some spare devices to sale cheap in EU, if you want one let me know! :-)

JTAGulator is an open source hardware tool, created by Joe Grand / Grand Idea Studio, that assists in identifying OCD connections from test points, vias, or component pads on a target device. All you need is a target device, bunch of tap wires / cables, USB-Mini cable, and serial terminal to operate JTAGulator.

On-chip debug (OCD) interfaces can provide chip-level control of a target device and are a primary vector used by engineers, researchers, and hackers to extract program code or data, modify memory contents, or affect device operation on-the-fly. Depending on the complexity of the target device, manually locating available OCD connections can be a difficult and time consuming task, sometimes requiring physical destruction or modification of the device.

I have started my works on implementing the Serial Wire Debug (kind of JTAG alternative for ARM-Cortex Cores) for Open-Source OpenOCD and UrJTAG utilities. You can watch the progress at:

http://stm32primer2swd.sf.net

Project type: Open
Status: Work in progress…