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wtorek, 20 luty 2007 |
Simple ALU written in Verilog, as a task on microelectronics basics course laboratory on my University.
Written using editor VIM, compiled by open-source CVER.
Status: Finished
Type: Open
pmk-lab6-tomek_cedro.v - source code
verilog.log - compilation result = testbench output
verilog.dump file graphical analysis:
GTK Wave screenshot - a free open-source timing analysis program. |
